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AK8136A ms1108 - e - 04 dec - 2013 - 1 - low power multiclock generator with vcxo AK8136A features 27mhz crystal input one 27mhz - reference output 2 wire serial register interface selectable clock out frequencies: - 148.352 , 148.5 mhz - 10 0. 7 1 , 108 mhz - 22.579 2 , 24.576, 33.8688, 36.864 mhz - 27.0mhz bui lt - in vcxo - pull range: 1 5 0ppm ( typ .) low jitter performance - period jitter: 150 psec (typ.) at clk 2 ,clk3 ,clk4 - tie 100 psec (max) at clk1p,clk1n - long term jitter 160 psec (typ.) at refout low current consumption: 3 2 m a (typ.) at 3.3v supply voltage: 3.0 C 3.6v operating temperature range: - 20 to +85 package: 20 - pin ssop (lead free , halogen free ) description the AK8136A is a member of ak m s low power multi clock generator family designed for a feature rich dtv or stb , requiring a ra nge of system clocks with high performance. the AK8136A generat es different frequency clocks f r o m a 27m hz crystal oscillator and provides them to up to four outputs configured by register - setting. the on - chip vcxo accepts a voltage control input to allow the output clocks to vary by 1 5 0 ppm for synchronizing to the external clock system. b oth circuitries of vcxo and pll in AK8136A are derived f r o m akm s long - term - experienced clock devic e technology , and enable clock output to perform low jitter and to operate with very low current consumption. the AK8136A is ava ilable in a 20 - pin ssop pa ckage. applicatio ns ? set - top - boxes AK8136A multi clock generator clk2 cl k3 clk4 refout vref gnd sda s c l voltage controlled crystal oscillator x i x o clk1p clk1n vdd pll1 pll2 pll 3 vin control r egister full pd
AK8136A dec - 2013 ms1108 - e - 04 - 2 - pin d escription s package: 20 - pin ssop (top view) pin no. pin name pin type description 1 x i ain crystal connection , connect to 27.000mhz crystal 2 gnd 3 pwr ground 3 3 vin ain vcxo c ontrol voltage i nput 4 gnd4 pwr ground 4 5 clk2 do clock output 2, see register description . in full power down or disable, this pin is l . 6 vdd2 pwr power s upply 2 7 gnd2 pwr ground 2 8 clk3 do clock output 3, see register description in full power down or disable, this pin is l . 9 clk4 do clock output 4, copy of clk3 see register description in full power down or disable, this pin is l . 10 vref ao vref pin connect 1uf capacitor. hi - z in full power down state. 11 gnd1 pwr ground 1 12 vdd1 pwr power s upply 1 13 clk1p do clock output 1, these are differential pair. see register description in full power down or disable, these pin s are l . 14 clk1n do 15 sda di/do serial data input and output p in. open drain. 16 scl di serial interface c lock input. 17 vddi pwr power supply for serial interface. 1.8v or 3.3v can be used. 18 refout do reference c lock o utput of vcxo based on 27.000mhz crystal in full power down or disable, this pin is l . 19 vdd3 pwr power s upply 3 20 xo ao crystal connection , connect to 27.000mhz crystal ordering information part number marking shipping packaging package temperature range AK8136A 813 6a tape and reel 20 - pin ssop - 20 to 85 20 19 18 17 1 6 15 14 13 12 11 xi gnd3 vin gnd4 clk2 vdd2 gnd2 clk3 clk 4 vref xo vdd3 refout vddi scl sda clk1n clk1p vdd1 gnd1 1 2 3 4 5 6 7 8 9 10
AK8136A ms1108 - e - 0 4 dec - 2013 - 3 - absolute maximum rating o ver operating free - air temperature range unless otherwise noted (1) items s ymbol ratings unit s upply v oltage vdd /vddi - 0.3 to 4.6 v input voltage vin vss - 0.3 to vdd+0.3 v input c urrent (any pins except supplies) i in 10 ma storage temperature tstg - 55 to 130 ? c note (1) stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. f unctional operation of the device at these or any other conditions beyond those indicated under reco mmended operating conditions is not implied. exposure to absolute - maximum - rating conditions for extended periods may affect device reliability. electrical par ameters are guaranteed only over the recommended operating temperature range. this device i s manufactured on a cmos process, therefore, generically susceptible to damage by excessive static voltage. failure to observe proper handling and installation procedures can cause damage . akm recommends that this device is handled with appropriate precau tions. recommended operation condition s parameter s ymbol conditions m in typ m ax unit operating t emperature ta - 2 0 85 ? c supply voltage 1 (1) vddi pin: vddi 1.7 3.6 v supply voltage 2 ( 2 ) vdd pin: vdd1,vdd2,vdd3 3.0 3.3 3.6 v output load conditio n cl1 p in : clk1p,clk1n see figure 1 output load capacitance cp1 pin: clk2,clk 3,clk4 15 pf cp2 pin: refout 25 pf note: (1) a decoupling capacitor for power supply line should be install ed close to vddi pin. (2)power to vdd1, vdd2, vdd3 require s to be supplied from a single source. a decoupling capacitor for power supply line should be install ed close to each vdd pin. esd sensitive device
AK8136A dec - 2013 ms1108 - e - 04 - 4 - dc characteristics vdd: over 3.0 to 3.6v, vddi:over 1.7 to 3.6v, ta: - 20 to +85 , 27mhz crystal, unless otherwise noted parameter symbol conditions min typ max unit high l evel i nput v oltage v ih pin: sda,scl 0. 7 vdd i v low l evel i nput v oltage v il pin: sda,scl 0. 3 vdd i v input c urrent 1 i l 1 pin: sda,scl - 1 0 +10 a l 2 p in : vin - 3 + 3 a oh pin: clk 2 - 4 , refout i oh = - 4 ma 0.8vdd v low level o utput voltage v ol pin: clk 2 - 4 , refout i o l = +4 ma 0. 2vdd v output impedance pin:clk1p,clk1n t a =25 vref voltage v ref pin:vref c vref =1 dd 1 no load clock out selection by note (1) vdd/vddi=3.3v, ta=25 dd 2 on load (2) clock out selection by note (1) vdd/vddi=3.3v, ta=25 dd pd full_pd = a
AK8136A ms1108 - e - 0 4 dec - 2013 - 5 - ac characteristics (clock signals) vdd : over 3.0 to 3. 6 v, vddi over 1.7 to 3.6v, ta : over - 20 to +85 , 27m h z crystal, unless otherwise not ed (1) pullable range depends on crystal characteristics, on - chip load capacitance, and stray capacity of pcb. typ . 1 5 0 ppm is applied to akm s authorized test condition. please contact us when you plan the use of other crystal unit. (2) measured with load capacitance of 25pf (3) measured with load capacitance of 15pf (4) measured with load condition shown in figure.1 (5) 3 ? in 10000 sampling or more (6) 16ms accumulat e with higher than 1 0g sa/ s . (7) 3 ? in 10000 sampling or more (8) refer to figure. 7 on clock enable and disable sequence. (9) time to settle output into 0.1% of specified frequenc y from full_pd is l . refer to figure. 6 on full power down sequence . (10) refer to figure.5 on power on reset sequence . parameter symbol conditions min typ max unit crystal c lock f requency f osc pin: xi,xo 27.0000 mhz output clock accuracy f accuracy pin: clk2 100.7 1 mhz relative to 27.0mhz 106.25 ppm vcxo pullable range (1) pr vcxo vin at over 0 to vdd v 150 ppm v cxo gain g vcxo vin range at 1.5v1.0v 150 ppm/v period j itter ( 5 ) jit _period pin: refout (2) , clk 2 - 4 (3) 15 0 (6 ( 6 ) jit _tie pin: clk1 (4) 100 p s long term jitter ( 7 ) jit _long pin: refout 1000 cycle delay 160 p s output c lock d uty cycle dtycyc pin: clk1p , n (4) fig ure .3 clk 2 - 4 (3) 45 50 55 % pin: refout (2) 40 50 60 % output clock slew rate slew _rise_fall pin: clk1p,n ( 4) fig ure .3 2.5 8.0 v/ns slew rate matching slew _ver pin: clk1p,n (4) fig ure .2 20 % differenti al output swing v _swing pin: clk1p,n (4) fig ure .3 300 mv crossing point voltage v _c r oss pin: clk1p,n (4) fig ure .2 300 550 mv variation of vcr s v _cross_delta pin: clk1p,n (4) fig ure .2 140 mv maximum output voltage v _ max pin: clk1p,n (4) fig ure .2 1 .15 v minimum output voltage v _ min pin: clk1p,n (4) fig ure .2 - 0.3 v output c lock r ise t ime t _r ise pin: clk 2 - 4 (3) 1. 0 3.0 ns pin: refout (2 ) 2.5 5.0 ns output c lock f all ti me t _ fall pin: clk 2 - 4 (3) 1. 0 3.0 ns pin: refout (2 ) 2.5 5.0 ns output enable/ disable time (8) t _en_dis pin: refout,clk 1 p,n clk2 - 4 500 ns power - up time 1 ( 9 ) t _pu t 1 pin: refout, clk 1 p,n clk2 - 4 4 ms power - up t ime 2 ( 10 ) t _pu t 2 pin: refout, clk 1 p,n clk2 - 4 150 ms
AK8136A dec - 2013 ms1108 - e - 04 - 6 - figure.1 clk1 load condition figure.2 single ended (se) measurement waveforms <5inch 2pf 30 ? +/ - 5% rs t - line z=5 0 ? t - line z=5 0 ? 2pf pll core vref 3 .3v measure point v_cross_m in=300mv v_cross_max=550mv v_max=1.15v v_min= - 0.3v v_cross clk1p clk1 n clk1 p clk1 n v_cross_delta_max=140mv v_cross_delta clk1 p clk1 n +75mv - 75mv v _ cross(avg) slew_rise se(avg) +75mv - 75mv slew_fall se(avg)
AK8136A ms1108 - e - 0 4 dec - 2013 - 7 - period clk1_diff clk1_diff 0.0v 0.0v 0.0v +dtycyc - dtycyc +150mv - 150mv v_swing slew_rise slew_fall figure. 3 differential ( diff ) measurement waveforms
AK8136A dec - 2013 ms1108 - e - 04 - 8 - ac characteristics ( serial interface vdd : over 3.0 to 3. 6 v, vdd i over 1.7 to 3.6v, ta : over - 20 to +85 , 27m h z crystal, unless otherwise noted figure.4 s erial interface timing parameter symbol conditions min max unit scl clock frequency fscl 400 khz scl clock low period tlow 1.3 s scl clock high period thigh 0.6 s pulse width of spikes wh ich must be suppressed ti 50 ns slc low to sda data out taa 0.3 s bus free time between a stop and start condition tbuf 1.3 s start condition hold time thd.sta 0.6 s start condition setup time (for a repeated start c ondition) tsu.sta 0.6 m s data in hold time thd.dat 0 s data in setup time tsu.dat 100 ns sda and scl rise time tr 0.3 s sda and scl fall time tf 0.3 s stop condition setup time tsu.sto 0.6 s bus line load cb 200 pf scl ( in ) sda ( in ) sda ( out ) tf tr tsu . sta thd . sta tsu . sto tsu . dat thd . dat taa tdh tbuf tlow thigh
AK8136A ms1108 - e - 0 4 dec - 2013 - 9 - function description power on reset sequence ak 8136a ha s the por(power on reset) circuit. in power up , the por works and the register is set to the initial value and all clock output becomes enable without glitch . not e 1) the a ssu mption power start time to reach 90 % of vdd is within 20 ms . not e 2) the first register setting should be done after the 150 ms elapse after the power on . figure .5 recommend power up sequence vdd1/2/3 p or (internal signal) register setting available scl/sda vdd*0.9 max : 20 ms min : 150 ms clk1p/clk2 - 4/refout clk1n
AK8136A dec - 2013 ms1108 - e - 04 - 10 - serial interface read/write performa nce of serial interface is expressed below. the device address #1 of AK8136A is fixed as 1010 . the device address #2 is 110 . device address of AK8136A byte wtire operation byte write operation is described below. data must be sent af ter sending 8 bits address and receiving ack. byte write page write operation page write operation is described below. only lower 4 bits of address are valid. upper 4 bits are fixed as 1111 . therefore the address which is written after 1111 1111 becomes 1111 111 0 . page write current address read current address read operation is described below. the data that is read by this operation is obtained as last accessed address + 1 . therefore, it is consequent to return 1111 111 0 after accessing the address 1111 1111 . current address read 1 0 1 0 1 1 0 r/w device adress#2 device adress#1 r:1 w:0 1 0 1 0 device address device address 0 r w address ( msb first ) data ( msb first ) s t a r t sda - 1 - 2 / a c k a c k a c k s t o p 1 1 0 device address device address r w address ( msb first ) data ( address ) s t a r t sda - 1 - 2 / a c k a c k a c k data a c k ( address + 1 ) 1 0 1 0 0 a c k s t o p data a c k ( address + n ) ???? 1 1 0 1 0 1 0 device address device address 1 r w data ( msb first ) s t a r t sda - 1 - 2 / a c k n o a s t o p c k 1 0 1
AK8136A ms1108 - e - 0 4 dec - 2013 - 11 - random read random read operation is described below. it is necessary to operate dummy write before sending read command . dummy write is to send the address to read. random read sequential read sequential read operation is described below. it is possible to read next address sequentially by sending ack instead of stop condition. sequentia l read change data change data operation is described below. it is available when scl is low. change data start / stop timing start / stop timing is described below. the sequence is started when sda goes from high to low during scl is high. the sequence is stopped when sda goes from low to high during scl is high. start / stop timing 1 0 1 0 device address device address 0 r w address ( msb first ) s t a r t sda - 1 - 2 / a c k a c k s t a r t 1 0 1 0 device address - 1 n o a s t o p c k dummy write device address 1 r w - 2 / a c k data ( msb first ) 1 0 1 1 0 1 sda device address 1 r w - 2 / a c k data ( msb first ) ( address ) n o a s t o p c k a c k data ( msb first ) ( address + 1 ) a c k ???? a c k data ( msb first ) ( address + n ) ???? 1 0 1 sda scl data stable data change sda scl start stop
AK8136A dec - 2013 ms1108 - e - 04 - 12 - register description the AK8136A generates a range of low - jitter and hi - accuracy cl ock frequencies with three built - in plls and provides to up to five assigned outputs. a frequency selection at assigned output pin and power down control is configured by register - setting. register map address d7 d6 d5 d4 d3 d2 d1 d0 note ff full_pd - - - clk3s[1] clk3s[0] clk2s clk1s 0 - - - 1 1 0 0 d efault fe clk4_dis clk3 _dis clk2_dis clk1 _dis ref_dis 0 0 0 0 0 d efault register definition full_pd (address ff:d7) power down control 0 device active ( pll on) enable vcxo, vr ef and plls (default) 1 full power down disable vcxo, vref and plls full p ower d own sequence the full power down setting is done by following sequence. 1) c hang e clkn_dis ( n =1,2,3,4) and ref_dis to "1" . 2) c hange full_pd to "1" from "0". t he output tran sfers to the disabled state without glitch. the full power down state is release d by following sequence. 1) c hang ing full_pd to " 0 " from "1" . 2) a fter more than 4 ms elapse , change clkn_dis and ref_dis " 0 " to " 1 " . t he output transfers to the enable state wit hout glitch . figure.6 full down sequence clkn_dis , ref_dis full_pd c lk1p/ clk2 - 4/ refout clk1n >4ms
AK8136A ms1108 - e - 0 4 dec - 2013 - 13 - clk3s[1:0 ] (address ff:d3,d2) clk3 &4 output frequency selection 00 22.5792mhz 01 24.576mhz 10 33.8688mhz 11 36.864mhz (default) clk2s (address ff:d1) clk2 output frequency selection 0 108mhz. (default) 1 100.71mhz clk1s (address ff:d 0 ) clk1 output frequency selection 0 148.5mhz/1.001 (default) 1 148.5mhz clk4_dis (address f e :d 7 ) clk4 output disable 0 enable (clk 4 active ) (default) 1 disable(clk 4= clk3_dis (address f e :d 6 ) clk3 output disable 0 enable (clk 3 active ) (default) 1 disable(clk 3= clk2_dis (address f e :d 5 ) clk2 output disable 0 enable (clk 2 active ) (default) 1 disable(clk 2 = clk1_dis (address f e :d 4 ) clk1 output disable 0 enable (clk 1 active ) (default) 1 disable(clk 1p,clk1n=
AK8136A dec - 2013 ms1108 - e - 04 - 14 - ref_dis (address f e :d 3 ) refout output disable 0 enable ( refout active ) (default) 1 disable( refout= clock enable and disable sequence the enabling and disabling of the clock output are executed without glitch within 500 ns from the rising edge of scl during the a c know le dge operation after the corresponding byte date reception. figure.7 output enable and disable sequence scl disable sda clkn refout scl sda clkn refout ack enable ack < 500ns < 500ns
AK8136A ms1108 - e - 0 4 dec - 2013 - 15 - voltage control led crystal oscillator (vcxo) the AK8136A has a voltage contro l l ed crystal oscillator (vcxo), featuring fine frequency tuning for 27mhz of primary clock frequency by external dc voltage cont rol. t his tuning enables output clock frequency to synchronize the external clock system. vin (pin 3 ) accepts dc voltage control from a processor or a system controller, and pulls the primary frequency of crystal to higher or lower. this pulling range is determined by crystal characteristic, on - chip load capacitor , and stray capacitance of pcb. the AK8136A is designed to range 1 5 0ppm of primary frequency in akm s authorized condition, and the typical pulling profile is shown in figure 8 . for details about the condition and other specific crystal application case, refer the ak813 6a applicatio n note . figure 8 : typical vcxo pulling profile 27mhz vcxo characteristics kds dsx530ga -200 -150 -100 -50 0 50 100 150 200 0 0.5 1 1.5 2 2.5 3 3.5
AK8136A dec - 2013 ms1108 - e - 04 - 16 - k ds dsx530ga item min typ max unit remark nominal frequency f0 27.000 mhz cl= 10.0pf equivalent resistance r1 50 spurious ? no spurious within 3fo13kh z ? with in f0500khz the attenuation of the sp urious response should be more than 3db. crystal unit load capacitance cl l1 r1 c1 c0 cl figure . 9 equivalent parameter and load capacitance
AK8136A ms1108 - e - 0 4 dec - 2013 - 17 - package information ? marking a: #1 pin index b: part number c: date code (5 digits) d product family logo (1) ? rohs complian ce all integrated circuits form asahi kasei microdevices corporation (akm) assembled in lead - free packages* are fully compliant with rohs. (*) rohs compliant products from akm are identified with pb free letter indication on product label posted on the anti - shield bag and boxes. 1 20 10 11 813 6 a xxxxx akm a b c d 1 1 0 1 1 2 0 6 . 5 + 0 . 3 0 - 0 . 1 0 4 . 4 0 0 . 2 0 0 . 1 0 0 . 1 0 0 . 1 0 1 . 1 5 0 . 1 0 s s 0 . 1 0 m 0 . 2 2 0 . 1 0 0 b 1 0 b 0 . 1 5 + 0 . 1 0 - 0 . 0 5 0 . 5 0 0 . 2 0 6 . 4 0 0 . 3 0 0 . 6 5 0 . 4 5 m a x
AK8136A dec - 2013 ms1108 - e - 04 - 18 - important notice 0. asah i kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes warranties or r epresentations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this docum ent. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily i njury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation , traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above use unless speci fically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and sy stems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact a km sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, includ ing without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technica l features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in wh ole or in part, without prior written consent of akm . 0.8max 1.60. 2

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